There is a storage apparatus which adopts a method in which data from a host computer is temporarily stored in a cache memory in accordance with an access request from the host computer, subsequently the data stored in the cache memory is stored in a storage device and, if the data requested in the read request from the host computer exists in the cache memory, the data stored in the cache memory is transferred to the host computer.
In this type of storage apparatus, for speeding up data transmission, a high-speed interface represented by, for example, PCI-Express (registered trademark) is sometimes used as an interface of the data transmission path connecting a micro-processor which controls the cache memory with a relay unit communicating data with the host computer or the storage device.
If the high-speed interface is used, the request side which issues a read request, a host computer for example, transmits a read request including a management number, a data transfer length, and an address as a packet to the response side. The response side, a microprocessor managing the cache memory for example, reads the data requested in the read request from the cache memory, applies the read data to the maximum transfer length of the high-speed interface, and transmits the same to the request side. Here, if the response side adopts split completion, the microprocessor on the response side splits the read data into a plurality of units by, for example, a 64 B (byte) boundary (address boundary) or a 128 B boundary, and sequentially transmits the split units of data to the request side in numerical order of the addresses.
For example, if the maximum transfer length of the high-speed interface is 1 kB and a 4 kB data is requested in a read request, the microprocessor on the response side splits the data read from the cache memory (the 4 kB data) into four or more units, adds each of the split data as a completion data equal to or smaller than 1 kB to a packet in numerical order of the addresses, and transmits the same.
Meanwhile, if Out Of Order is adopted on the response side, each time a read request is received from the request side, the microprocessor on the response side can split the data requested in each of the read requests into a plurality of units of data and transmit each of the split data to the request side in random order regardless of the order of reception of the respective read requests.
However, the data which is split in accordance with the same read request is sequentially transmitted to the request side in numerical order of the addresses.
In this case, if the microprocessor on the response side accepts a second read request after receiving a first read request and a 4 kB data is required respectively by each of the read requests, the microprocessor on the response side can read the data requested in each of the read requests from the cache memory, split each of the read data (4 kB data) into 1 kB units, and transmit each of the split data as a 1 kB completion data to the request side in random order regardless of the order of reception of the respective read requests.
For example, each of the data requested in the first read request and the data requested in the second read request can be alternately transmitted as a 1 kB completion data. Furthermore, after the data requested in the second read request is transmitted as a 1 kB completion data, it is also possible to transmit the data requested in the first read request as a 1 kB completion data.
Furthermore, as an apparatus using a high-speed interface, for example, a communication apparatus comprising a transmission circuit which transmits transmission data to the other destination, a receiver circuit which receives received data from the other destination, a storage device as a transfer buffer which performs buffering for the transmission data and receiver buffer which performs buffering for the reception data, and an address mapping means for performing address mapping for the transmission buffer and the receiver buffer in the storage device and changing the storage capacity of each of the transmission buffer and the reception buffer is proposed (refer to Patent Literature 1).